sycan.components.active.mosfet_l1¶
Shichman-Hodges Level 1 MOSFET, polarity-aware (NMOS / PMOS).
The model equations below are written in “effective” form. With
pol = +1 for NMOS, -1 for PMOS V_GS_eff = pol * (V(gate) - V(source)) V_DS_eff = pol * (V(drain) - V(source))
the conduction condition in both cases is V_GS_eff > V_TH and
V_DS_eff >= V_GS_eff - V_TH. The threshold V_TH is stored as
a positive magnitude for both polarities.
DC drain current (saturation + channel-length modulation):
I_D_mag = (1/2) * mu_n * Cox * (W/L)
* (V_GS_eff - V_TH)**2 * (1 + lam * V_DS_eff)
I_D_SPICE = pol * I_D_mag # current INTO drain (SPICE sign)
For NMOS this is the usual positive I_D; for PMOS it is negative (the device pulls current out of the drain externally).
AC small-signal model — obtained by differentiating I_D_SPICE
at (V_GS_op, V_DS_op) with sympy.diff():
g_m = dI_D/dV_GS|_OP
g_ds = dI_D/dV_DS|_OP
Gate capacitances C_gs / C_gd are stamped as s*C
admittances in AC mode. Bulk is tied to source (three-terminal).
Concrete classes NMOS_L1 and PMOS_L1 fix
polarity via typing.ClassVar; users pick one in their
netlist / Python API.
Classes
|
Shichman-Hodges Level 1 NMOS (saturation region). |
|
Shichman-Hodges Level 1 PMOS (saturation region). |
- class sycan.components.active.mosfet_l1.NMOS_L1(name, drain, gate, source, mu_n, Cox, W, L, V_TH, lam=<factory>, C_gs=<factory>, C_gd=<factory>, V_GS_op=None, V_DS_op=None, KF=<factory>, AF=<factory>, EF=<factory>, *, include_noise=None)[source]¶
Bases:
_MOSFET_L1Shichman-Hodges Level 1 NMOS (saturation region).
- Parameters:
name (str)
drain (str)
gate (str)
source (str)
mu_n (Expr)
Cox (Expr)
W (Expr)
L (Expr)
V_TH (Expr)
lam (Expr)
C_gs (Expr)
C_gd (Expr)
V_GS_op (Expr | None)
V_DS_op (Expr | None)
KF (Expr)
AF (Expr)
EF (Expr)
include_noise (None | str | list[str] | tuple[str, ...] | frozenset[str])
- polarity: ClassVar[str] = 'N'¶
- class sycan.components.active.mosfet_l1.PMOS_L1(name, drain, gate, source, mu_n, Cox, W, L, V_TH, lam=<factory>, C_gs=<factory>, C_gd=<factory>, V_GS_op=None, V_DS_op=None, KF=<factory>, AF=<factory>, EF=<factory>, *, include_noise=None)[source]¶
Bases:
_MOSFET_L1Shichman-Hodges Level 1 PMOS (saturation region).
- Parameters:
name (str)
drain (str)
gate (str)
source (str)
mu_n (Expr)
Cox (Expr)
W (Expr)
L (Expr)
V_TH (Expr)
lam (Expr)
C_gs (Expr)
C_gd (Expr)
V_GS_op (Expr | None)
V_DS_op (Expr | None)
KF (Expr)
AF (Expr)
EF (Expr)
include_noise (None | str | list[str] | tuple[str, ...] | frozenset[str])
- polarity: ClassVar[str] = 'P'¶